1. Technical Field
Various embodiments of the present invention relate to a semiconductor apparatus and, more particularly, to an address output timing control circuit of a semiconductor apparatus.
2. Related Art
When a read or write command is inputted to a semiconductor apparatus (e.g., a semiconductor memory), the semiconductor apparatus provides an address to a corresponding circuit configuration after a period of time predefined according to the operation specification related to the read or write command.
For example, the operation specification related to a read command includes a CAS latency (CL) and a burst length (BL). The operation specification related to a write command includes a CAS latency (CL), a burst length (BL), and a CAS write latency (CWL).
As illustrated in FIG. 1, a conventional control circuit 1 for controlling address output timing includes a plurality of flip-flops DFF, a plurality of latches, and a logic circuit 10. The logic circuit 10 may include a NAND gate.
The plurality of flip-flops DFF shift a write command WRITE to conform to a CAS latency, a burst length, and a CAS write latency. The plurality of latches latch a column address TLA<0>, in response to the shifted write command WRITE, to conform to the CAS latency, the burst length, and the CAS write latency and output the latched column address TLA<0> to the logic circuit 10.
By performing a NAND operation on the outputs of the plurality of latches, the logic circuit 10 output a column address ATCD<0> whose timing has been adjusted based on the CAS latency, the burst length, and the CAS write latency.
Although not illustrated in FIG. 1, the control circuit 1 may also require a circuit configuration for a read command READ that outputs the corresponding column address for the read command READ by applying timings corresponding to the CAS latency and the burst length.
Thus, the conventional control circuit 1 for controlling address output timing control circuit 1 employs a method in which the write and read commands and their respective addresses are sequentially shifted to comply with the CAS latency, burst length, and CAS write latency specifications.
The CAS latency may have a value of 5 to 16, the burst length may have a value of 4 or 8 (for DDR3), and the CAS write latency may have a value of 5 to 12. Consequently, twenty-two flip-flops and twenty-two latches are required so that the column address TLA<0> for the write command WRITE can have the timing according to the preset specification. This is equally applicable to a read command READ.
Accordingly, since the conventional control circuit 1 for controlling address output timing requires the plurality of latches and the plurality of flip-flops, the circuit area may increase.
Furthermore, the CAS latency, the burst length, and the CAS write latency will likely further increase with the advancement in the technological development and speed of semiconductor memories, which may worsen the above-described area problem.